2023
doi: 10.12720/jait.14.3.479-487
Efficient FPGA-Based Convolutional Neural Network Implementation for Edge Computing
Cuong Pham-Quoc1,2,*
,
- 1Department of Computer Engineering, Ho Chi Minh City University of Technology (HCMUT), Ho Chi Minh City, Vietnam
- 2Department of Computer Engineering, Vietnam National University, Ho Chi Minh City (VNU-HCM), Ho Chi Minh City, Vietnam
- Manuscript receivedJanuary 16, 2023
- revisedMarch 2, 2023
- acceptedApril 5, 2023
- publishedMay 24, 2023
Abstract
In recent years, accelerating convolutional neural networks on Field Programmable Gate Array (FPGA) to improve the performance of the inference phase of artificial intelligent edge computing applications is a promising approach. This paper presents our proposed architecture for building a convolution neural network acceleration core on FPGA. The proposed FPGA-based core targets edge computing platforms where hardware resources and power efficiency are essential requirements. We use the MobileNet neural network model for image classification as a case study to evaluate our proposed system. We compare our work with a quad-core ARM Cortex processor at 1.2GHz and achieve speed-ups by up to 14.77× convolution operators. Although our system is worse than a 6-core Intel Core i7 processor, it is more energy-efficiency than the Intel processor. Our proposed system is the best fit for edge computing.
Keywords
- Field Programmable Gate Array (FPGA)
- convolutional neural network
- hardware accelerator
- MobileNet
How to Cite
Cuong Pham-Quoc and Tran Ngoc Thinh, "Efficient FPGA-Based Convolutional Neural Network Implementation for Edge Computing," Journal of Advances in Information Technology, vol. 14, no. 3, pp. 479-487, 2023. https://doi.org/10.12720/jait.14.3.479-487
Copyright & License
Copyright © 2023 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
