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JAIT 2024 Vol.15(2): 195-201
doi: 10.12720/jait.15.2.195-201

Efficient Random Forest Acceleration for Edge Computing Platforms with FPGA Technology

Cuong Pham-Quoc 1,2,*,, Trung Pham-Dinh 1,2, and Binh Kieu-Do-Nguyen 3
1. Department of Computer Engineering, Faculty of Computer Science and Engineering, Ho Chi Minh City University of Technology (HCMUT), Ho Chi Minh City, Vietnam
2. Department of Computer Engineering, Vietnam National University-Ho Chi Minh City (VNU-HCM), Thu Duc, Ho Chi Minh City, Vietnam
3. Very Large-Scale Integration (VLSI) Lab, University of Electro-Communications (UEC), Tokyo, Japan
Email: cuongpham@hcmut.edu.vn (C.P.-Q.); trung.pham.ktmt@hcmut.edu.vn (T.P.-D.); binh@vlsilab.ee.uec.ac.jp (B.K.-D.-N.)
*Corresponding author

Manuscript received on June 25, 2023 , revised July 11, 2023; accepted August 17, 2023; published February 5, 2024.

Abstract—As one of the most successful instances of ensemble learning algorithms, Random Forest offers many advantages compared to other approaches. However, it is unsuitable for edge computing platforms due to its high computational power. In this paper, we present our proposed efficient architecture to perform random forest effectively for edge computing platforms based on Field Programmable Gate Array (FPGA) technology. The heart of the system is our Decision Tree Unit (DTU) architecture, which is mainly responsible for processing decision trees in the pipeline to achieve better performance. One of the biggest obstacles to decision tree implementation on hardware is the memory size. In this paper, we also propose a sufficient structure for storing decision trees’ information for the execution of DTUs. Since we target edge computing platforms with limited resources and energy, the architecture supports the scalability of the number of DTUs in the system. Based on the available resources of the target platform, the system can be reconfigured accordingly. We implement our prototype version with the PYNQ Z2 FPGA edge computing board. We test the proposed system with the number of DTUs changed from 1 to 15. We conduct experiments and analysis with a certified dataset and compare with Intel core i7 and core i9 processors to show our efficiency and scalability. The experimental results show that we can achieve speed-ups by up to 19.96x compared to the Intel Core i7 desktop version and 12x compared to the Intel Core i9 high-performance computing version. Regarding energy consumption, we save up to 33.24x and 146.24x compared to the two processors.
Keywords—Field Programmable Gate Array (FPGA) technology, decision tree, random forest acceleration, edge computing platforms

Cite: Cuong Pham-Quoc, Trung Pham-Dinh, Binh Kieu-Do-Nguyen, "Efficient Random Forest Acceleration for Edge Computing Platforms with FPGA Technology," Journal of Advances in Information Technology, Vol. 15, No. 2, pp. 195-201, 2024.

Copyright © 2024 by the authors. This is an open access article distributed under the Creative Commons Attribution License (CC BY-NC-ND 4.0), which permits use, distribution and reproduction in any medium, provided that the article is properly cited, the use is non-commercial and no modifications or adaptations are made.