Abstract—As one of the most successful instances of ensemble learning algorithms, Random Forest offers many advantages compared to other approaches. However, it is unsuitable for edge computing platforms due to its high computational power. In this paper, we present our proposed efficient architecture to perform random forest effectively for edge computing platforms based on Field Programmable Gate Array (FPGA) technology. The heart of the system is our Decision Tree Unit (DTU) architecture, which is mainly responsible for processing decision trees in the pipeline to achieve better performance. One of the biggest obstacles to decision tree implementation on hardware is the memory size. In this paper, we also propose a sufficient structure for storing decision trees’ information for the execution of DTUs. Since we target edge computing platforms with limited resources and energy, the architecture supports the scalability of the number of DTUs in the system. Based on the available resources of the target platform, the system can be reconfigured accordingly. We implement our prototype version with the PYNQ Z2 FPGA edge computing board. We test the proposed system with the number of DTUs changed from 1 to 15. We conduct experiments and analysis with a certified dataset and compare with Intel core i7 and core i9 processors to show our efficiency and scalability. The experimental results show that we can achieve speed-ups by up to 19.96x compared to the Intel Core i7 desktop version and 12x compared to the Intel Core i9 high-performance computing version. Regarding energy consumption, we save up to 33.24x and 146.24x compared to the two processors.
 
Keywords—Field Programmable Gate Array (FPGA) technology, decision tree, random forest acceleration, edge computing platforms


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