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28 Nanometers FPGAs Support for High Throughput and Low Power Cryptographic Applications

Yaser Jararweh1, Lo'ai Tawalbeh1, Hala Tawalbeh1, and Abidalrahman Moh’d2
1. Cryptographic Hardware and information Security lab (CHiS) Jordan University of Science and Technology, Irbid, Jordan
2. Engineering Mathematics and Internetworking Dalhousie University, Halifax, Canada
Abstract—The current unprecedented advancements of communication systems and high performance computing urged for a high throughput applications with power consumption within a predefined budget. These advancements were accompanied with a crucial need for securing such systems and users critical data. Current cryptographic applications suffer from the limitations of their low throughput and extensive power consumption that severely impact the available power budget. Creating new algorithms to handle these issues will be a time consuming process. One viable solution is to use the new 28 Nanometers (nm) FPGAs devices that promise to provide less power consumption with a very competitive throughput and throughput to area ratio comparing to the older technologies. In this paper, we evaluate the 28 nm FPGAs technology and its impact in eight of the major cryptographic algorithms available today such as SHA2, SHA3, and AES. Our results revealed that using the 28 nm FPGAs reduced the power consumption to more than 50% and increase the throughput up to 100% compared to the older FPGs technologies. On the other hand, throughputs to area ratio results show about 71% improvement over other technologies.

Index Terms—Hardware Evaluation, Power, Throughput, FPGA, 28 nm technology, AES, SHA

Cite: Yaser Jararweh, Lo'ai Tawalbeh, Hala Tawalbeh, and Abidalrahman Moh’d, "28 Nanometers FPGAs Support for High Throughput and Low Power Cryptographic Applications," Journal of Advances in Information Technology, Vol. 4, No. 2, pp. 84-90, May, 2013.doi:10.4304/jait.4.2.84-90
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